本帖最后由 蓝子风 于 2017-1-15 04:09 编辑
本来我说的意思只是二级锁相能做的很好,也能做的很一般的意思。
嗯,对于8XR和DA1/2的原理,真不清楚呢,麻烦大神说说吧~~~本菜洗耳恭听。
SYNCHRONIZATION | Multi-stage, auto-ranging PLL per Path | Ultra-high-precision mode | (+/- 0.15%) | Jitter rejection corner frequency | ~80Hz | Jitter rejection slope | 60dB / decade | Jitter attenuation | >60dB above 700Hz | High-precision mode | (+/- 6.0%) | Internal | 32, 44.1, 48, 88.2, 96, 176.4, 192 kHz +/-25ppm | Each path can be separately synchronized. Path sampling rate can be frequency-locked to a different reference frequency, for example: 96kHz path locked to 48kHz Worldclock. |
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